In recent LSI processes, miniaturization has progressed, thus the wiring width of LSI has been reduced and LSI speed has also progressed.
Accordingly, the impact of a wiring line on propagation delay has become significant. Therefore, in a conventional LSI, in order to reduce the differences in the propagation delay time, circuit layout designs are carried out so as to have the same signal path lengths as much as possible.
FIG. 17 is a circuit diagram showing the structure of a conventional 4-input multiplexer.
In FIG. 17, each of the transmission gates TG21 to TG28 has an input terminal, an output terminal, a selection-signal input terminal, and an inverted-signal input terminal, individually.
The transmission gates TG21 and TG22 are connected in cascade, the transmission gates TG23 and TG24 are connected in cascade, the transmission gates TG25 and TG26 are connected in cascade, and the transmission gates TG27 and TG28 are connected in cascade.
An input signal A enters the transmission gate TG21, an input signal B enters the transmission gate TG23, an input signal C enters the transmission gate TG25, an input signal D enters the transmission gate TG27, and the output terminals of the transmission gates TG22, TG24, TG26, and TG28 are commonly connected, and an output signal OUT is output therefrom.
Also, a selection input signal S1 enters the selection-signal input terminal of the transmission gate TG21, an inverted signal S1B of the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG21; a selection input signal S2 enters the selection-signal input terminal of the transmission gate TG22, an inverted signal S2B of the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG22; the selection input signal S1 enters the selection-signal input terminal of the transmission gate TG23, the inverted signal S1B of the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG23; the inverted signal S2B of a selection input signal S2 enters the selection-signal input terminal of the transmission gate TG24, the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG24; the inverted signal S1B of the selection input signal S1 enters the selection-signal input terminal of the transmission gate TG25, the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG25; the selection input signal S2 enters the selection-signal input terminal of the transmission gate TG26, the inverted signal S2B of the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG26; the inverted signal S1B of the selection input signal S1 enters the selection-signal input terminal of the transmission gate TG27, the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG27; the inverted signal S2B of the selection input signal S2 enters the selection-signal input terminal of the transmission gate TG28, and the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG28.
Then, when a 2-bit selection input signal (S1, S2)=(1, 1), the transmission gates TG21 and TG22 turn on to output the input signal A as the output signal OUT; when a 2-bit selection input signal (S1, S2)=(1, 0), the transmission gates TG23 and TG24 turn on to output the input signal B as the output signal OUT; when a 2-bit selection input signal (S1, S2)=(0, 1), the transmission gates TG25 and TG26 turn on to output the input signal C as the output signal OUT; and when a 2-bit selection input signal (S1, S2)=(0, 0), the transmission gates TG27 and TG28 turn on to output the input signal D as the output signal OUT.
FIG. 18 is a circuit diagram showing the structure of a conventional 4-output demultiplexer.
In FIG. 18, each of the transmission gates TG31 to TG38 has an input terminal, an output terminal, a selection-signal input terminal, and an inverted-signal input terminal, individually.
The transmission gates TG31 and TG32 are connected in cascade, the transmission gates TG33 and TG34 are connected in cascade, the transmission gates TG35 and TG36 are connected in cascade, and the transmission gates TG37 and TG38 are connected in cascade.
Also, the input terminals of the transmission gates TG31, TG33, TG35, and TG37 are commonly connected, an input signal IN enters the input terminals of the transmission gates TG31, TG33, TG35, and TG37, at the same time, the transmission gate TG32 outputs an output signal A, the transmission gate TG34 outputs an output signal B, the transmission gate TG36 outputs an output signal C, and the transmission gate TG38 outputs an output signal D.
Also, a selection input signal S1 enters the selection-signal input terminal of the transmission gate TG31, an inverted signal S1B of the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG31; a selection input signal S2 enters the selection-signal input terminal of the transmission gate TG32, an inverted signal S2B of the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG32; the selection input signal S1 enters the selection-signal input terminal of the transmission gate TG33, the inverted signal S1B of the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG33; the inverted signal S2B of the selection input signal S2 enters the selection-signal input terminal of the transmission gate TG34, the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG24; the inverted signal S1B of the selection input signal S1 enters the selection-signal input terminal of the transmission gate TG35, the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG35; the selection input signal S2 enters the selection-signal input terminal of the transmission gate TG36, an inverted signal S2B of the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG36; the inverted signal S1B of the selection input signal S1 enters the selection-signal input terminal of the transmission gate TG37, the selection input signal S1 enters the inverted-signal input terminal of the transmission gate TG37; the inverted signal S2B of the selection input signal S2 enters the selection-signal input terminal of the transmission gate TG38, and the selection input signal S2 enters the inverted-signal input terminal of the transmission gate TG38.
Then when a 2-bit selection input signal (S1, S2)=(1, 1), the transmission gates TG31 and TG32 turn on to output the input signal IN as the output signal A; when a 2-bit selection input signal (S1, S2)=(1, 0), the transmission gates TG33 and TG34 turn on to output the input signal IN as the output signal B; when a 2-bit selection input signal (S1, S2)=(0, 1), the transmission gates TG35 and TG36 turn on to output the input signal IN as the output signal C; and when a 2-bit selection input signal (S1, S2)=(0, 0), the transmission gates TG37 and TG38 turn on to output the input signal IN as the output signal D.
However, in the multiplexer shown in FIG. 17, when disposing the transmission gates TG21 to TG28 on a silicon substrate, and taking out the output signal OUT at the middle of the output nodes of the transmission gates TG22, TG24, TG26 and TG28, a wiring length of taking out the input signals A and D as the output signal OUT becomes longer as compared with a wiring length of taking out the input signals B and C as the output signal OUT.
Consequently, the propagation delay of the input signals A and D becomes larger than that of the input signals B and C. Thus, there has been a problem in that every time the output signal OUT is switched by the selection input signal (S1, S2), jitters (fluctuations of edges) arise corresponding to the difference s in the propagation time of the input signals A to D.
If the circuit layout design is changed such that the wiring lengths become the same when taking out the input signals A to D as the output signal OUT, design work becomes bothersome. Moreover, when the number of input signals is large, the design change is not realistic.
Also, in the method of using a low resistance process such as copper wiring in order to reduce the propagation delay, there has been a problem in that the cost is increased, and if the difference in wiring length is too large, the difference in the propagation delay time cannot be eliminated.
Similarly, the same problems exist in the demultiplexer shown in FIG. 18.
Accordingly, one aspect of the present invention is to provide an output circuit, an input circuit, an electronic circuit, a multiplexer, a demultiplexer, a wired-OR circuit, a wired-AND circuit, a pulse-processing circuit, a multiphase-clock processing circuit, and a clock-multiplier circuit which are capable of having substantially the same propagation delay time for each signal path, without designing the circuit layout to have the same wiring length, and without using a low resistance process.